1 of 7 092702 features 1024 bits of read/write memory low data retention current for battery backup applications four million bits/second data rate single-byte or multiple-byte data transfer capability no restrictions on the number of write cycles low-power cmos circuitry applications software authorization computer identification system access control secure personnel areas calibration automatic system setup traveling work record pin assignment pin description v cc - +5v rst - reset dq - data input/output clk - clock gnd - ground v bat - battery (+) nc - no connection description the ds1200 serial ram chip is a miniature read/write memory th at can randomly access individual 8-bit strings (bytes) or sequentially access the entir e 1024-bit contents (burst). interface cost to a microprocessor is minimized by on-chip circuitry, wh ich permits data transfers with only three signals: clk, rst , and dq. nonvolatility can be achieved by connecting a battery of 2v to 4v at the battery input v bat. a load of 0.5 should be used to size the external battery for the required data retention time. if nonvolatility is not required the v bat pin should be grounded. 16-pin so (300mil) see mech. drawings section ds1200 serial ram chip www.maxim-ic.com
ds1200 2 of 7 figure 1. electronic tag block diagram figure 2. address/command operation the block diagram (figure 1) illustrates the main elements of the device: shift register, control logic, nv ram, and power switch. to initiate a memory cycle, rst is taken high and 24 bits are loaded into the shift register, providing both address and command information. e ach bit is input serially on the rising edge of the clk input. seven address bits specify one of the 128 ram locations. the remaining command bits specify read/write and byte/burst mode . after the first 24 clocks, which load the shift register, additional clocks will output data for a read or input data for a write. the number of clock pulses equal 24 plus 8 for byte mode or 24 plus 1024 for burst mode. for hardwired applications, active power is supplied by the v cc pin. alternatively, for user-insertable applications, power can be supplied by the rst pin.
ds1200 3 of 7 address/command each memory transfer consists of a 3-byte input called the address/command. the address/command is shown in figure 2. as defined, the first byte of the address/command specifies whether the memory is written or read. if any one of the bits of the first byte of the address/command fail to meet the exact pattern of read or write, the cycle is aborted and all future inputs to the tag are ignored until rst is brought low and then high again to begin a new cycle. the 8-bit pattern for read is 10011101. the second byte of the address/command describes address inputs a0 in bit 0 thr ough a6 in bit 6. bit 7 of the second byte of the address/command word mu st be set to logic 0. if bit 7 does not equal logic 0, the cycle is aborted and all future inputs to the tag are ignored until rst is brought low and then high again to begin a new cycle. the third byte of the address/command (bits 0 through 6) must be set to logic 0 or the cycle is aborted and all future inputs are ignored until rst is brought low and then high again to begin a new cycle. bit 7 of byte 3 of the address/command is used along with address bits a0 through a6 to define burst mode. when a0 through a6 equals logic 0 and bit 7 of byte 3 of the address command equals logic 1, the tag will enter the burst mode after the address/command sequence is complete. burst mode burst mode is when all address bits (a0 to a6) of the address/command are set to logic 0 and bit 7 of byte 3 to logic 1. the burst mode causes 128 consecutive bytes to be read or written. burst mode terminates when the rst input is driven low. reset and clock control all data transfers are initiated by driving the rst input high. the rst input serves three functions. first, rst turns on the control logic, which allows access to the shift register for the address/command sequence. second, the rst signal provides a power source fo r the cycle to follow. to meet this requirement, a drive source for rst of 2ma at 3.8v is required. however if the v cc pin is connected to a 5v source within nominal limits, then the rst pin is not used as a sour ce of power and input levels revert to normal v ih and v il inputs with a drive current requirement of 500 . finally, the rst signal provides a method of terminating either single byte or multiple byte data transfers. a clock cycle is a sequence of falling edge followed by a rising edge. for data inputs, the data must be valid during the rising edge of the clock cycle. address/command bits and data bits are input on the rising edge of the clock and data bits are output on the falling edge of the clock. all data transfer terminates if the rst input is low and dq pin goes to a hi gh-impedance state. when data transfer to the serial ram chip is terminated using, rst , the transition of rst must occur while the clock is at high level to avoid disturbing the last bit of data. data transfer is illustrated in figure 3. data input following the 24 clock cycles that input an address/ command, a data byte is input on the rising edge of the next eight clock cycles, assuming that the read/write and write/read bits are properly set (for data input byte 1, bit 0 = 1; bit 1 = 0; bit 2 = 1; bit 3 = 1; bit 4 = 1; bit 5 = 0; bit 6 = 0; bit 7 = 1). data output following the 24 clock cycles that input the read mode, a data byte is output on the falling edge of the next eight clock cycles (for data output byte 1, bit 0 = 0; bit 1 = 1; bit 2 = 0; bit 3= 0; bit 4 = 0; bit 5 = 1; bit 6 = 1; bit 7 = 0).
ds1200 4 of 7 figure 3. data transfer notes: 1) data input sampled on rising edge of clock cycle. 2) data output changes on falling edge of clock.
ds1200 5 of 7 figure 4. read/write data transfer
ds1200 6 of 7 absolute maximum rating* voltage range on any pin relative to ground -1.0v to +7.0v operating temperature range 0 c to +70 c storage temperature range -40 c to +70 c * this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. recommended dc operating conditions (0 c to +70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v 1, 2, 10 logic 0 v il -0.3 0.8 v 1 rst logic 1 v ihe 3.8 1, 7, 11 power supply voltage v cc 4.5 5.0 5.5 v 1 battery voltage v bat 2.0 4.0 v 1 dc electrical characteristics (0 c to +70 c; v cc = 5v 10%) parameter symbol min typ max units notes input leakage i l +500 a 5 output leakage i lo +500 a 5 output current at 2.4v i oh -1 ma output current at 0.4v i ol +2 ma rst input resistance z rst 10 40 k ? 1 dq input resistance z dq 10 40 k ? 1 clk input resistance z clk 10 40 k ? 1 active current i cc1 6ma8 standby current i cc2 2.5 ma 8 rst current i rst 2 ma 7, 8, 13 capacitance (t a = +25c) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf
ds1200 7 of 7 ac electrical characteristics (0oc to +70oc; v cc = 5v 10%) parameter symbol min typ max units notes data to clk setup t dc 35 ns 3, 9 data to clk hold tcdh 40 ns 3, 9 data to clk delay t cdd 125 ns 3, 4, 6, 9 clk low time t cl 125 ns 3, 9 clk high time t ch 125 ns 3, 9 clk frequency f clk dc 4.0 mhz 3, 9 clk rise and fall t r , t f 500 ns 9 rst to clock setup t cc 1s3, 9 clk to rst hold t cch 40 ns 3, 9 rst inactive time t cwh 125 ns 3, 9, 14 rst to i/o high-z t cdz 50 ns 3, 9 notes: 1) all voltages and resistances are referenced to ground. 2) input levels apply to clk, dq, and rst while v cc is not connected to the tag, then rst input reverts to v ihe . 3) measured at v ih = 2.0 or v il = 0.8v and 10ns maximum rise and fall time. 4) measured at v oh = 2.4v and v ol = 0.4v. 5) for clk, dq, rst , and v cc at 5v. 6) load capacitance = 50pf. 7) applies to rst when v cc < 3.8v. 8) measured with outputs open. 9) measured at vih of rst greater than or equal to 3.8v when rst supplies power. 10) logic 1 maximum is v cc + 0.3v if the v cc pin supplies power and rst +0.3v if the rst pin supplies power. 11) rst logic 1 maximum is v cc + 0.3v if the v cc pin supplies power a nd 5.5v maximum if rst supplies power. 12) each ds1200 is marked with a four-digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined as starting at the date of manufacture. 13) average ac rst current can be determined using the following formula: i total = 2 + i load dc + (4 x 10 -3 )(cl + 140)f i total and i load are in ma; cl is in pf; f is in mhz. applying the above formula, a load capacitance of 50pf running at a frequency of 4.0mhz gives an i total current of 5ma. 14) when rst is supplying power, t cwh must be increased to 100ms.
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